Electroformed wafer-bumping stencils from Tecan Stencils Limited (TSL), are being used to accurately deposit solder paste directly onto silicon wafer die - following a re-flow operation, the paste forms the conductive solder bumps required for I/O.

Highly accurate and repeatable results are offered by the stencils which allow users to cost-effectively maximise the available yield from a given wafer. The stencil apertures have very smooth walls, with a trapezoidal cross-section, which ensure optimum paste release characteristics - improving the consistency of solder paste volume and hence, ball size and regularity.

The stencils cater for the increasingly high component densities and pitches associated with components such as chip-scale packages (CSPs), micro ball-grid arrays (BGA's) and flip-chip designs. For example, a typical stencil for a multi-die six-inch wafer may require 300,000 apertures, or over 500,000 for an eight-inch wafer, with hole diameters of 60 to 125 microns.

The technology represents a significant step forward in the reduction of production costs for such increasingly miniaturised silicon substrate electronics components. It also ensures compatibility with existing SMT processes.

Process control is a fundamental element in the success of CSP, BGA and similar packaging. The adoption of TSL electroformed stencils provides the ability to tightly control each assembly process to ensure repeatable high yields.

Designs can be submitted as CAD files and the company offers a maximum five-day
Despatch prototyping service. The following CAD formats are accepted, Gerber (RS274X), GWK, DPF and HPGL. All parts are produced within the company's strict ISO9002 quality-control regime.

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